Test apparatus and semiconductor chip

ABSTRACT

A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. The test apparatus may include a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data. The turnaround delay detection value may be generated by detecting a time of from a point of time when write data including a read command as the reference data is output to a point of time when the read data is received.

CROSS-REFERENCES TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119(a) to Koreanapplication No. 10-2016-0024360, filed on Feb. 29, 2016, in the Koreanintellectual property Office, which is incorporated by reference in itsentirety as set forth in full.

BACKGROUND

1. Technical Field

Various embodiments may generally relate to a semiconductor integratedcircuit, and more particularly, to a test apparatus for testing asemiconductor chip.

2. Related Art

Test apparatuses for testing a data input/output (I/O) operation of asemiconductor chip, for example, a memory chip may store write data inthe memory chip. As such, a determination may be made on whether thememory chip has passed or failed by comparing read data output from thememory chip according to a read command with the write data storedtherein.

A delay time of from a point of time when the read command is generateto a point of time when the read data is input may refer to a turnarounddelay (TAD).

An asynchronous delay component is included in the turnaround delay. Theasynchronous delay may be influenced by variation in power, voltage, andtemperature, and thus the turnaround delay value may be changed. Sincethe test apparatus may have no information for the variation of theturnaround delay, the reliability of the test operation may be degraded.

SUMMARY

According to an embodiment, a test apparatus may be provided. The testapparatus may include a delay compensator configured to generate delayedread data by delaying read data according to a difference between anexternal turnaround delay value provided externally from the testapparatus and a turnaround delay detection value detected within thetest apparatus. The test apparatus may include a determination circuitconfigured to perform a test result determination operation by comparingthe delayed read data with reference data. The turnaround delaydetection value may be generated by detecting a time of from a point oftime when write data including a read command as the reference data isoutput to a point of time when the read data is received.

According to an embodiment, a test apparatus may be provided. The testapparatus may include a tester configured to set a delay compensationtime of read data by detecting a turnaround delay of from a first pointof time when write data including a read command is output in aturnaround delay compensation mode to a second point of time when theread data received exteriorly from the test apparatus is received,generate delayed read data by delaying the read data by the delaycompensation time in a normal test mode, and perform a test resultdetermination operation by comparing the delayed read data with thewrite data as reference data.

According to an embodiment, a test apparatus for a semiconductor chipmay be provided. The test apparatus may include a delay compensatorconfigured to generate delayed read data by delaying read data accordingto a difference between an external turnaround delay value providedexternally from the test apparatus and a turnaround delay detectionvalue detected within the test apparatus. The test apparatus may includea determination circuit configured to perform a test resultdetermination operation by comparing the delayed read data withreference data. The turnaround delay detection value may be generated bydetecting a time of from a point of time when write data including aread command as the reference data is output to the semiconductor chipto a point of time when the read data is input from the semiconductorchip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating a representation of an example of aconfiguration of a test chip according to an embodiment.

FIG. 2 is a view for explaining an example of a turnaround delayaccording to the test chip of FIG. 1.

FIG. 3 is a view illustrating a representation of an example of aconfiguration of a tester of FIG. 1.

FIG. 4 is a view illustrating a representation of an example of aconfiguration of a delay compensator of FIG. 3.

FIG. 5 is a view illustrating a representation of an example of aconfiguration of a controller of FIG. 4.

DETAILED DESCRIPTION

Hereinafter, examples of embodiments will be described below withreference to the accompanying drawings. Examples of embodiments aredescribed herein with reference to cross-sectional illustrations thatare schematic illustrations of examples of embodiments (and intermediatestructures). As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but may be toinclude deviations in shapes that result, for example, frommanufacturing. In the drawings, lengths and sizes of layers and regionsmay be exaggerated for clarity. Like reference numerals in the drawingsdenote like elements. It is also understood that when a layer isreferred to as being “on” another layer or substrate, it can be directlyon the other or substrate, or intervening layers may also be present.

The concepts are described herein may be discussed with reference tocross-section and/or plan illustrations that are schematic illustrationsof various embodiments. However, the embodiments should not be construedas limiting. Although a few embodiments will be illustrated anddescribed, it will be appreciated by those of ordinary skill in the artthat changes may be made in these examples of embodiments withoutdeparting from the principles and spirit of the disclosure.

One or more examples of embodiments may be provided to a test apparatuscapable of compensating a turnaround delay according to a chip to betested.

Referring to FIG. 1, a test chip 100 as a test apparatus according to anembodiment may be coupled to a chip to be tested, for example, a memorychip 101 through a plurality of channels, for example, a first channel102 and a second channel 103.

The test chip 100 may include a plurality of path circuits (for example,a first path circuit 210 and a second path circuit 220) and a tester400.

The first path circuit 210 may transmit write data DOUT<0:3> to thememory chip 101 through the first channel 102.

An example of the write data DOUT<0:3> that a burst length is ‘4’ isillustrated in FIG. 1.

The write data DOUT<0:3> may include a command, for example, a readcommand or a write command.

A corresponding bit among bits constituting the write data DOUT<0:3> maybe set to a predetermined value, and thus the memory chip 101 mayrecognize the write data DOUT<0:3> as the command, for example, the readcommand or the write command.

The first path circuit 210 may include a serializer 211, a delay 212,and a transmitter (TX) 213.

The serializer 211 may serialize the write data DOUT<0:3> and output theserialized write data.

The delay 212 may delay an output of the serializer 211 by a preset timeand output the delayed output of the serializer 211.

The transmitter 213 may transmit an output of the delay 212 to the firstchannel 102.

The second path circuit 220 may transmit the read data DIN<0:3>transmitted from the memory chip 101 to the tester 400 through thesecond channel 103.

The second path circuit 220 may include a receiver (RX) 221, a delay222, and a parallelizer 223.

The receiver 221 may receive data transmitted through the second channel103 and output the received data.

The delay 222 may delay an output of the receiver 221 by a preset timeand output the delayed output of the receiver 221.

The parallelizer 223 may parallelize an output of the delay 222 andinput the parallelized output of the delay 222 as the read data DIN<0:3>to the tester 400.

The tester 400 may include, for example, an algorithmic patterngenerator (ALPG) (not illustrated).

The tester 400 may delay the read data DIN<0:3> according to adifference between an external turnaround delay value TAD_EX providedfrom the outside of the test apparatus 100 and a turnaround delaydetection value generated by detecting a time of from a point of timewhen the write data DOUT<0:3> including the read command is output tothe semiconductor chip 101 to a point of time when the read dataDIN<0:3> output from the semiconductor chip 101 is input, and determinea pass or fail of the memory chip 101 by comparing the delayed read datawith the write data. The semiconductor chip 101 may be realized with amemory chip 101 or include a memory chip 101.

The time of from a point of time when the write data DOUT<0:3> is outputfrom the tester 400 to a point of time when the write data DOUT<0:3> isinput to the tester 400 via the first path circuit 210, the firstchannel 102, the memory chip 101, the second channel 103, and the secondpath circuit 220 may refer to the turnaround delay TAD.

The turnaround delay TAD may be divided into a delay time tTX accordingto the first path circuit 210, a delay time tCH according to the firstchannel 102, a delay time tCH according to the second channel 103, adelay time tRX according to the second path circuit 220, and a readlatency RL, which is a delay time of from a point of time when thememory chip 101 recognizes a read command RD (RD not illustrated) fromthe write data DOUT<0:3> to a point of time when the memory chip 101outputs actual data, according to a component.

Referring to FIG. 2, the turnaround delay TAD according to an embodimentmay be defined as TAD=tTX+2*tCH+RL+tRX.

The tester 400 according to an embodiment may autonomously detect theturnaround delay TAD, compensate the delay time of the read dataDIN<0:3> using the detected turnaround delay value as the turnarounddelay detection value, and determine a pass or fail of the memory chip101 by comparing the delayed read data with the write data.

Referring to FIG. 3, the tester 400 may include a delay compensator 500and a determination circuit 600.

The delay compensator 500 may generate delayed read data DIN_DLY bydelaying read data DIN according to a difference between the externalturnaround delay value TAD_EX and the turnaround delay detection valuegenerated by detecting a time of from a point of time when write dataDOUT including the read command RD is output to the memory chip 101 to apoint of time when the read data DIN is input from the memory chip 101.

The delay compensator 500 may generate the delayed read data DIN_DLYaccording to a calibration enable signal CAL_EN, the write data DOUT,the read data DIN, a clock signal CLK, and the external turnaround delayvalue TAD_EX.

The determination circuit 600 may generate a determination signal PASSwhich defines pass or fail of the memory chip 101 by comparing thedelayed read data DIN_DLY with the write data DOUT.

Referring to FIG. 4, the delay compensator 500 may include a delaycircuit 501, a multiplexer 502, a register 503, period signal generators504 and 505, and a controller 506.

The delay circuit 501 may generate a plurality of delay signals 0D to 3Dby delaying the read data DIN according to the clock signal CLK.

The read data DIN may be any one of DIN<0:3>.

The delay circuit 501 may include a plurality of flip flops DFF.

The plurality of flip flops DFF may generate the plurality of delaysignals 0D to 3D by shifting the read data DIN or an output of aprevious flip flop DFF according to the clock signal CLK.

The multiplexer 502 may select one among the plurality of delay signals0D to 3D and output the selected delay signal as the delayed read dataDIN_DLY according to a control signal CTRLD.

The register 503 may store the turnaround delay value provided from theoutside of the test apparatus 100, that is, the external turnarounddelay value TAD_EX.

The period signal generators 504 and 505 may generate a first periodsignal START_CNT and a second period signal END_CNT according to thecalibration enable signal CAL_EN, the write data DOUT, and the read dataDIN.

The period signal generators 504 and 505 may include a first logic gate504 and a second logic gate 505.

The first logic gate 504 may output the first period signal START_CNT toa high level when the write data DOUT is transit to a high level in astate that the calibration enable signal CAL_EN has an activation level(that is, high level).

The second logic gate 505 may output the second period signal END_CNT toa high level when the read data DIN is transit to a high level in astate that the calibration enable signal CAL_EN has a high level.

The timing that an input terminal of the first logic gate 504 whichreceives the write data DOUT is transit to a high level may be an outputtiming of the write data DOUT.

The timing that an input terminal of the second logic gate 505 whichreceives the read data DIN is transit to a high level may be an inputtiming of the read data DIN.

The delay time of from a point of time when the first period signalSTART_CNT is transit to a high level to a point of time when the secondperiod signal END_CNT is transit to a high level may refer to an actualturnaround delay TAD.

The controller 506 may detect the turnaround delay according to thefirst and second period signals START_CNT and END_CNT and the clocksignal CLK, and generate the control signal CTRLD according to thedifference between the external turnaround delay value TAD_EX and thedetected turnaround delay value.

Referring to FIG. 5, the controller 506 may include a latch 510, acounter 520, and an operator 530.

The latch 510 may generate a counting enable signal CNT_EN according tothe first and second period signals START_CNT and END_CNT.

The latch 510 may activate the counting enable signal CNT_EN accordingto activation of the first period signal START_CNT and inactivate thecounting enable signal CNT_EN according to activation of the secondperiod signal END_CNT.

The counter 520 may detect the turnaround delay by counting the clocksignal CLK according to the counting enable signal CNT_EN.

The counter 520 may output a counting value of the clock signal CLKcorresponding to an activation period of the counting enable signalCNT_EN as the turnaround delay detection value TAD_CAL.

The operator 530 may output an operation result value for a differencebetween the external turnaround delay value TAD_EX and the turnarounddelay detection value TAD_CAL as the control signal CTRLD.

An operation of the test apparatus 100 having an above-describedconfiguration according to an embodiment will be described.

Referring to FIG. 1, the tester 400 may perform a write operation. Thatis, the tester 400 may perform data write on the memory chip 101 byoutputting data having a predetermined pattern together with the writecommand.

Referring to FIG. 4, after the write operation, the tester 400 may enterthe turnaround delay compensation mode by activating the calibrationenable signal CAL_EN to a high level.

The tester 400 may output the write data DOUT<0:3> including the readcommand RD to the memory chip 101 in the turnaround delay compensationmode.

As the write data DOUT<0:3> is output in a state that the calibrationenable signal CAL_EN is a high level, that is, as a level of apredetermined bit among the bits constituting the write data DOUT<0:3>is transit to a high level, the first period signal START_CNT may beactivated to a high level.

Referring to FIG. 5, as the first period signal START_CNT is transit toa high level, the counting enable signal CNT_EN may be activated.

As the counting enable signal CNT_EN is activated, the counter 520 maystart to count the clock signal CLK.

Referring to FIG. 1, the memory chip 101 may output the read dataDIN<0:3> by recognizing the read command RD included in the write dataDOUT<0:3>.

Referring to FIG. 4, as the read data DIN<0:3> is input to the tester400, that is, as a level of a predetermined bit among the bitsconstituting the read data DIN<0:3> is transit to a high level, thesecond period signal END_CNT may be activated to a high level.

Referring to FIG. 5, as the second period signal END_CNT is transit to ahigh level, the counting enable signal CNT_EN may be inactivated.

The counter 520 may output a counting value of the clock signal CLKwhich is a value of from a point of time when the counting enable signalCNT_EN is activated to a point of time when the counting enable signalCNT_EN is inactivated as the turnaround delay detection value TAD_CAL.

The operator 530 may perform an operation on the difference between theexternal turnaround delay value TAD_EX and the turnaround delaydetection value TAD_CAL and output an operation result value as thecontrol signal CTRLD.

The delay compensation time of the read data DIN<0:3> may be determinedaccording to the control signal CTRLD.

The tester 400 may enter the normal test mode by inactivating thecalibration enable signal CAL_EN to a low level when a predeterminedtime elapsed after the second period signal END_CNT is activated.

When the read data DIN<0:3> according to the read command RD is input inthe normal test mode, the delay compensator 500 may generate the delayedread data DIN_DLY by delaying the read data DIN<0:3> by a predeterminedtime through the delay circuit 501 and provide the delayed read dataDIN_DLY to the determination circuit 600 according to the control signalCTRLD.

The determination circuit 600 may generate the pass signal PASS whichdefines pass or fail of the memory chip 101 by comparing the delayedread data DIN_DLY with the write data DOUT.

The above embodiments are illustrative and not limitative. Variousalternatives and equivalents are possible. The disclosure is not limitedby the embodiments described herein. Nor is the disclosure limited toany specific type of semiconductor device. Other additions,subtractions, or modifications are obvious in view of the presentdisclosure and are intended to fall within the scope of the appendedclaims.

What is claimed is:
 1. A test apparatus comprising: a delay compensatorconfigured to generate delayed read data by delaying read data accordingto a difference between an external turnaround delay value providedexternally from the test apparatus and a turnaround delay detectionvalue detected within the test apparatus; and a determination circuitconfigured to perform a test result determination operation by comparingthe delayed read data with reference data, wherein the turnaround delaydetection value is generated by detecting a time of from a point of timewhen write data including a read command as the reference data is outputto a point of time when the read data is received.
 2. The test apparatusof claim 1, wherein the test apparatus is coupled to a first channel anda second channel, the test apparatus further comprising: a first pathcircuit configured to transmit the write data to the first channel; anda second path circuit configured to transmit the read data transmittedthrough the second channel to the delay compensator.
 3. The testapparatus of claim 2, wherein the first path circuit includes: aserializer configured to serialize the write data and output serializedwrite data; and a transmitter configured to transmit an output of theserializer to the first channel.
 4. The test apparatus of claim 2,wherein the second path circuit includes: a receiver configured toreceive the read data; and a parallelizer configured to parallelize anoutput of the receiver and transmit the parallelized output of thereceiver to the delay compensator.
 5. The test apparatus of claim 1,wherein the delay compensator includes: a delay circuit configured togenerate a plurality of delay signals by delaying the read data; amultiplexer configured to select one among the plurality of delaysignals and output the selected delay signal as the delayed read dataaccording to a control signal; a period signal generator configured togenerate a period signal according to a calibration enable signal, thewrite data, and the read data; and a controller configured to generatethe turnaround delay detection value according to the period signal anda clock signal and generate the control signal according to the externalturnaround delay value and the turnaround delay detection value.
 6. Thetest apparatus of claim 5, wherein the period signal generator includes:a first logic gate configured to generate a first period signalaccording to the calibration enable signal and the write data; and asecond logic gate configured to generate a second period signalaccording to the calibration enable signal and the read data.
 7. Thetest apparatus of claim 5, wherein the controller includes: a latchconfigured to generate a counting enable signal according to the periodsignal; a counter configured to output a counting value of the clocksignal as the turnaround delay detection value according to the countingenable signal; and an operator configured to output an operation resultvalue for a difference between the external turnaround delay value andthe turnaround delay detection value as the control signal.
 8. The testapparatus of claim 5, wherein the delay circuit includes a plurality offlip flops configured to shift the read data or an output of a previousflip flop according to the clock signal.
 9. A test apparatus comprising:a tester configured to set a delay compensation time of read data bydetecting a turnaround delay of from a first point of time when writedata including a read command is output in a turnaround delaycompensation mode to a second point of time when the read data receivedexteriorly from the test apparatus is received, generate delayed readdata by delaying the read data by the delay compensation time in anormal test mode, and perform a test result determination operation bycomparing the delayed read data with the write data as reference data.10. The test apparatus of claim 9, wherein the tester enters theturnaround delay compensation mode by activating a calibration enablesignal.
 11. The test apparatus of claim 9, wherein the tester enters thenormal test mode by inactivating the calibration enable signal.
 12. Thetest apparatus of claim 9, wherein the tester includes: a delay circuitconfigured to generate a plurality of delay signals by delaying the readdata; a multiplexer configured to select one of the plurality of delaysignals and output the selected delay signal as the delayed read dataaccording to a control signal; a period signal generator configured togenerate a period signal which defines a period of from the first pointof time to the second point of time according to a calibration enablesignal, the write data, and the read data; and a controller configuredto generate a turnaround delay detection value corresponding to theturnaround delay according to the period signal and a clock signal andgenerate the control signal according to an external turnaround delayvalue and the turnaround delay detection value.
 13. The test apparatusof claim 12, wherein the delay circuit includes a plurality of flipflops configured to shift the read data or an output of a previous flipflop according to the clock signal.
 14. The test apparatus of claim 12,wherein the period signal generator includes: a first logic gateconfigured to generate a first period signal activated at the firstpoint of time according to the calibration enable signal and the writedata; and a second logic gate configured to generate a second periodsignal activated at the second point of time according to thecalibration enable signal and the read data.
 15. The test apparatus ofclaim 12, wherein the controller includes: a latch configured togenerate a counting enable signal according to the period signal; acounter configured to output a counting value of the clock signal as theturnaround delay detection value according to the counting enablesignal; and an operator configured to output an operation result valuefor a difference between the external turnaround delay value and theturnaround delay detection value as the control signal.
 16. The testapparatus of claim 9, wherein the test apparatus is coupled to a firstchannel and a second channel, the test apparatus further comprising: afirst path circuit configured to transmit the write data to the firstchannel; and a second path circuit configured to transmit the read datatransmitted through the second channel to the tester.
 17. The testapparatus of claim 16, wherein the first path circuit includes: aserializer configured to serialize the write data and output serializedwrite data; and a transmitter configured to transmit an output of theserializer to the first channel.
 18. The test apparatus of claim 16,wherein the second path circuit includes: a receiver configured toreceive the read data; and a parallelizer configured to parallelize anoutput of the receiver and transmit the parallelized output of thereceiver to the tester.
 19. A test apparatus for a semiconductor chip,the test apparatus comprising: a delay compensator configured togenerate delayed read data by delaying read data according to adifference between an external turnaround delay value providedexternally from the test apparatus and a turnaround delay detectionvalue detected within the test apparatus; and a determination circuitconfigured to perform a test result determination operation by comparingthe delayed read data with reference data, wherein the turnaround delaydetection value is generated by detecting a time of from a point of timewhen write data including a read command as the reference data is outputto the semiconductor chip to a point of time when the read data is inputfrom the semiconductor chip.